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? semiconductor components industries, llc, 2011 june, 2011 ? rev. 3 1 publication order number: ncp3011/d ncp3011, ncv3011 synchronous pwm controller the ncp3011 is a pwm device designed to operate from a wide input range and is capable of producing an output voltage as low as 0.8 v. the ncp3011 provides integrated gate drivers and an internally set 400 khz oscillator. the ncp3011 has an externally compensated transconductance error amplifier with an internally fixed soft ? start. the ncp3011 incorporates output voltage monitoring with a power good pin to indicate that the system is in regulation. the dual function sync pin synchronizes the device to a higher frequency (slave mode) or outputs a 180 out ? of ? phase clock signal to drive another ncp3011 (master mode). protection features include lossless current limit and short circuit protection, output overvoltage and undervoltage protection, and input undervoltage lockout. the ncp3011 is available in a 14 ? pin tssop package. features ? input voltage range from 4.7 v to 28 v ? 400 khz operation ? 0.8 v 1.0% reference voltage ? buffered external +1.25 v reference ? current limit and short circuit protection ? power good ? enable/disable pin ? input undervoltage lockout ? external synchronization ? output overvoltage and undervoltage protection ? ncv prefix for automotive and other applications requiring site and change controls ? this is a pb ? free device typical applications ? set top box ? power modules ? asic / dsp power supply vin vcc bst hsdr vsw lsdr gnd fb comp en pg vref sync c bst q2 q1 lo r iset rfb1 c o r c c c2 cin c c1 r fb2 v out r ref cref figure 1. typical application circuit tssop ? 14 dt suffix case 948g marking diagram http://onsemi.com 3011= device code a = assembly location l = wafer lot y = year w = work week = pb ? free package 1 14 3011 alyw 1 14 vref en nc sync pg comp fb hsdr vcc bst vsw nc lsdr gnd pin connections (top view) device package shipping ? ordering information ncp3011dtbr2g tssop ? 14 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. (note: microdot may be in either location) NCV3011DTBR2G tssop ? 14 (pb ? free) 2500 / tape & reel
ncp3011, ncv3011 http://onsemi.com 2 gate drive logic vc clk/ dmax/ soft start oov boost clamp level shift sample & hold vc hsdr lsdr gnd ? + ? + ? + vcc comp fb ref ramp oscillator bst vsw vcc figure 2. ncp3011 block diagram pg en sync vref internal bias iset 1.5 v bst_chrg enable/ power good logic thermal sd por/startup 1.25 v reference ota pwm comp ouv current limit
ncp3011, ncv3011 http://onsemi.com 3 pin function description pin pin name description 1 vref the vref pin is the output for a 1.25 v reference (1 ma max). a 100 k resistor in parallel with a 1 f ceramic capacitor must be connected from this pin to gnd to ensure external reference stability. 2 en the en pin is the enable/disable input. a logic high on this pin enables the device. this pin has also an internal current source pull up. a 10 k resistor should be connected in series with this pin if v en is externally biased from a separate supply. 3 nc not connected 4 sync the dual function sync pin synchronizes the device to a higher frequency (slave mode). alternately, it outputs a 456 khz clock signal with 180 of phase shift (master mode). connect a 100 k resistor from sync to gnd to enable master mode. no resistor is required for slave mode. 5 pg the power good pin is an open drain output that is low when the regulated output voltage is beyond the ?power good? upper and lower thresholds. otherwise, it is a high impedance pin. 6 comp the comp pin connects to the output of the operational transconductance amplifier (ota) and the positive terminal of the pwm comparator. this pin is used in conjunction with the fb pin to compensate the voltage mode control feedback loop. 7 fb the fb pin is connected to the inverting input of the ota. this pin is used in conjunction with the comp pin to compensate the voltage mode control feedback loop. 8 gnd ground pin 9 lsdr the lsdr pin is connected to the output of the low side driver which connects to the gate of the low side n ? fet. it is also used to set the threshold of the current limit circuit (i set ) by connecting a resistor from lsdr to gnd. 10 nc not connected 11 vsw the vsw pin is the return path for the high side driver. it is also used in conjunction with the v cc pin to sense current in the high side mosfet. 12 hsdr the hsdr pin is connected to the output of the high side driver which connects to the gate of the high side n ? fet. 13 bst the bst pin is the supply rail for the gate drivers. a capacitor must be connected between this pin and the vsw pin. 14 v cc the v cc pin is the main voltage supply input. it is also used in conjunction with the vsw pin to sense current in the high side mosfet.
ncp3011, ncv3011 http://onsemi.com 4 absolute maximum ratings (measured vs. gnd pin 8, unless otherwise noted) rating symbol v max v min unit high side drive boost pin bst 45 ? 0.3 v boost to v sw differential voltage bst ? v sw 13.2 ? 0.3 v comp comp 5.5 ? 0.3 v enable en 5.5 ? 0.3 v feedback fb 5.5 ? 0.3 v high ? side driver output hsdr 40 ? 0.3 v low ? side driver output lsdr 13.2 ? 0.3 v power good pg 5.5 ? 0.3 v synchronization sync 5.5 ? 0.3 v main supply voltage input v cc 40 ? 0.3 v external reference vref 5.5 ? 0.3 v switch node voltage v sw 40 ? 0.6 v maximum average current v cc , bst, hsdrv, lsdrv, v sw , gnd ref en sync pg i max 130 7.1 2.5 11 4 ma operating junction temperature range (note 1) t j ? 40 to +140 c maximum junction temperature t j(max) +150 c storage temperature range t stg ? 55 to +150 c thermal characteristics (note 2) tssop ? 14 plastic package thermal resistance junction ? to ? air r ja 190 c/w lead temperature soldering (10 sec): reflow (smd styles only) pb ? free (note 3) r f 260 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the maximum package power dissipation limit must not be exceeded. p d t j(max) t a r ja 2. when mounted on minimum recommended fr ? 4 or g ? 10 board 3. 60 ? 180 seconds minimum above 237 c.
ncp3011, ncv3011 http://onsemi.com 5 electrical characteristics ( ? 40 c < t j < +125 c, v cc = 12 v, for min/max values unless otherwise noted) characteristic conditions min typ max unit input voltage range ? 4.7 28 v supply current quiescent supply current en = 0 v cc = 12 v ? 2.5 4.0 ma v cc supply current v fb = 0.75 v, switching, v cc = 4.7 v ? 5.8 8.0 ma v cc supply current v fb = 0.75 v, switching, v cc = 28 v ? 6.0 12 ma under voltage lockout uvlo rising threshold v cc rising edge 3.8 4.3 4.7 v uvlo falling threshold v cc falling edge 3.6 4.0 4.3 v oscillator oscillator frequency t j = +25 c, 4.7 v v cc 28 v 350 400 450 khz t j = ? 40 c to +125 c, 4.7 v v cc 28 v 330 400 470 khz ramp ? amplitude voltage v peak ? v alley ? 1.5 ? v ramp valley voltage 0.44 0.7 0.96 v pwm minimum duty cycle ? 7 ? % maximum duty cycle 80 83 ? % soft start ramp time v fb = v comp ? 5.2 ? ms external voltage reference vref voltage i ref = 1 ma 1.14 1.25 1.35 v vref line regulation v cc = 4.7 v ? 28 v ? 1 ? +1 % vref load regulation i ref = 0 ma to 1.5 ma ? 2 ? 0.2 +2 % short circuit output current v ref = 0 v 4.5 5.7 7.0 ma enable enable threshold high ? ? 3.4 v enable threshold low 1.0 ? ? v enable source current 20 50 90 a power good power good high threshold v cc = 12 v 0.72 0.89 1.06 v power good low threshold v cc = 12 v 0.65 0.71 0.75 v power good low voltage v cc = 12 v, i pg = 4 ma 0.13 0.22 0.35 v sync sync input high threshold ? ? 2.0 v sync output high 10 a load ? 5.0 ? v sync output low ? 90 ? mv phase delay (note 4) ? 200 ? sync drive current (sourcing) ? 1.6 ? ma master threshold current 5.0 14.4 25 a master frequency 390 466 550 khz 4. guaranteed by design. 5. the voltage sensed across the high side mosfet during conduction. 6. this assumes 100 pf capacitance to ground on the comp pin and a typical internal r o of > 10 m . 7. this is not a protection feature.
ncp3011, ncv3011 http://onsemi.com 6 electrical characteristics ( ? 40 c < t j < +125 c, v cc = 12 v, for min/max values unless otherwise noted) characteristic unit max typ min conditions error amplifier (gm) transconductance 0.9 1.33 1.9 ms open loop dc gain (notes 4 and 6) ? 70 ? db output source current output sink current 45 45 70 70 100 100 a a fb input bias current ? 0.5 500 na feedback voltage t j = 25 c ? 40 c < t j < +125 c, 4.7 v < v in < 28 v 0.792 0.788 0.8 0.8 0.808 0.812 v v comp high voltage v fb = 0.75 v 4.0 4.4 5.0 v comp low voltage v fb = 0.85 v ? 60 ? mv output voltage faults feedback oov threshold 0.9 1.0 1.1 v feedback ouv threshold 0.55 0.59 0.65 v over current iset source current 7.0 14 18 a current limit set voltage (note 5) r set = 22.2 k 140 240 360 mv gate drivers and boost clamp hsdrv pullup resistance v cc = 8 v and v bst = 7.5 v v sw = gnd 100 ma out of hsdr pin 4.0 10.5 20 hsdrv pulldown resistance v cc = 8 v and v bst = 7.5 v v sw = gnd 100 ma into hsdr pin 2.5 5.0 11.5 lsdrv pullup resistance v cc = 8 v and v bst = 7.5 v v sw = gnd 100 ma out of lsdr pin 3.0 8.9 16 lsdrv pulldown resistance v cc = 8 v and v bst = 7.5 v v sw = gnd 100 ma into lsdr pin 1.0 2.8 6.0 hsdrv falling to lsdrv rising delay v cc and v bst = 8 v 50 85 110 ns lsdrv falling to hsdrv rising delay v cc and v bst = 8 v 60 85 120 ns boost clamp voltage v in = 12 v, v sw = gnd, v comp = 1.3 v 5.5 7.5 9.6 v thermal shutdown thermal shutdown (notes 4 and 7) ? 150 ? c hysteresis (notes 4 and 7) ? 15 ? c 4. guaranteed by design. 5. the voltage sensed across the high side mosfet during conduction. 6. this assumes 100 pf capacitance to ground on the comp pin and a typical internal r o of > 10 m . 7. this is not a protection feature.
ncp3011, ncv3011 http://onsemi.com 7 typical performance characteristics figure 3. efficiency vs. output current and input voltage figure 4. load regulation vs. input voltage figure 5. feedback reference voltage vs. input voltage and temperature figure 6. switching frequency vs. input voltage and temperature i out (a) 6 3 2 1 0 60 65 70 75 80 85 90 95 efficiency (%) 4 i out (a) 6 3 2 1 0 3.31 3.32 3.33 3.34 3.35 v out (v) 4 temperature ( c) 125 110 50 5 ? 40 792 794 796 798 800 802 806 v fb (mv) v in = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 temperature ( c) 125 110 50 5 ? 40 340 360 380 400 420 440 460 f sw (khz) v in = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v in = 5 v 16 v 12 v 9 v 16 v 12 v 9 v v in = 5 v typical application circuit figure 47 typical application circuit figure 47 figure 7. supply current vs. input voltage and temperature figure 8. supply current (disabled) vs. input voltage and temperature temperature ( c) 125 110 50 5 ? 40 4.0 4.5 5.0 5.5 6.0 6.5 i cc , switching ( m a) v in = 28 v ? 25 ? 10 20 35 65 80 95 7.0 v in = 12 v v in = 5 v 5 5 804 temperature ( c) 125 110 50 5 ? 40 1.0 1.2 1.4 1.6 1.8 2.0 i cc , disabled (ma) v in = 28 v ? 25 ? 10 20 35 65 80 95 2.2 v in = 12 v v in = 5 v 2.4 2.6 2.8 3.0
ncp3011, ncv3011 http://onsemi.com 8 typical performance characteristics figure 9. transconductance vs. input voltage and temperature figure 10. input undervoltage lockout vs. temperature figure 11. output voltage thresholds vs. input voltage and temperature temperature ( c) 125 110 50 5 ? 40 1.24 1.255 1.27 1.285 1.30 1.315 1.33 gm (ms) v in = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v in = 5 v 1.345 1.36 1.375 1.39 temperature ( c) 12 5 110 50 5 ? 40 3.9 4.0 4.1 4.2 4.3 4.4 uvlo (v) uvlo rising threshold ? 25 ? 10 20 35 65 80 95 temperature ( c) 125 110 50 5 ? 40 500 600 700 800 threshold voltage (mv) ? 25 ? 10 20 35 65 80 95 900 1100 uvlo falling threshold pg_upper, v in = 5 ? 28 v pg_lower, v in = 5 ? 28 v figure 12. power good output low voltage vs. input voltage and temperature temperature ( c) 12 5 110 50 5 ? 40 150 175 200 225 250 275 300 v pg (mv) v in = 5, 12, 28 v ? 25 ? 10 20 35 65 80 95 i pg = 4 ma figure 13. enable thresold vs. input voltage and temperature figure 14. enable pullup current vs. input voltage and temperature 1000 325 350 temperature ( c) 125 110 50 5 ? 40 1.0 1.25 1.5 1.75 2.0 2.25 2.5 v en (v) v in = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v in = 5 v 2.75 3.0 3.25 3.5 rising threshold falling threshold v in = 12 v, 28 v v in = 5 v temperature ( c) 125 110 50 5 ? 40 30 35 40 45 50 55 60 i en ( a) v in = 5, 12, 28 v ? 25 ? 10 20 35 65 80 95 65 70 oov, v in = 5 ? 28 v ouv, v in = 5 ? 28 v
ncp3011, ncv3011 http://onsemi.com 9 typical performance characteristics figure 15. sync threshold vs. input voltage and temperature temperature ( c) 125 110 50 5 ? 40 1.0 1.2 1.4 1.6 1.8 2.0 v sync (v) v in = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v in = 5 v figure 16. valley voltage vs. input voltage and temperature temperature ( c) 125 110 50 5 ? 40 400 450 500 550 600 650 700 valley voltage (mv) ? 25 ? 10 20 35 65 80 95 750 800 850 900 v in = 5 ? 28 v 950 1000 input = 16 v, output = 3.3 v, load = 5 a c1 (blue) = vsw, c2 (light blue) = v out c3 (magenta) = power good, c4 (green) = enable figure 17. external reference voltage vs. input voltage and temperature temperature ( c) 125 110 50 5 ? 40 1.23 1.235 1.24 1.245 1.25 1.255 1.26 v refe (v) v in = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v in = 5 v figure 18. external reference voltage vs. input voltage and temperature figure 19. soft ? start waveforms figure 20. soft ? stop waveforms temperature ( c) 125 110 50 5 ? 40 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 v refe_load ? reg (%) ? 25 ? 10 20 35 65 80 95 0.4 0.6 0.8 1.0 v in = 5 v v in = 12 v, 28 v input = 16 v, output = 3.3 v, load = 5 a c1 (blue) = vsw, c2 (light blue) = v out c3 (magenta) = power good, c4 (green) = enable
ncp3011, ncv3011 http://onsemi.com 10 typical performance characteristics figure 21. soft ? start time vs. input voltage and temperature figure 22. current limit set current vs. temperature figure 23. no load switching waveforms (v in = 9 v) figure 24. ccm switching waveforms (v in = 9 v) figure 25. no load switching waveforms (v in = 16 v) temperature ( c) 125 110 50 5 ? 40 5.0 5.2 5.4 5.6 5.8 6.0 t soft ? start (ms) v in = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v in = 5 v temperature ( c) 125 110 50 5 ? 40 13.0 13.2 13.4 13.6 13.8 14.0 i set ( a) v in = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v in = 5 v input = 9 v, output = 3.3 v, load = 0 a c1 (blue) = vsw, c2 (light blue) = v out c3 (magenta) = hsdr figure 26. ccm switching waveforms (v in = 16 v) input = 9 v, output = 3.3 v, load = 5 a c1 (blue) = vsw, c2 (light blue) = v out c3 (magenta) = hsdr input = 16 v, output = 3.3 v, load = 0 a c1 (blue) = vsw, c2 (light blue) = v out c3 (magenta) = hsdr input = 16 v, output = 3.3 v, load = 5 a c1 (blue) = vsw, c2 (light blue) = v out c3 (magenta) = hsdr
ncp3011, ncv3011 http://onsemi.com 11 detailed description overview the ncp3011 operates as a 400 khz, voltage ? mode, pulse ? width ? modulated, (pwm) synchronous buck converter. it drives high ? side and low ? side n ? channel power mosfets. the ncp3011 incorporates an internal boost circuit consisting of a boost clamp and boost diode to provide supply voltage for the high side mosfet gate driver. the ncp3011 also integrates several protection features including input undervoltage lockout (uvlo), output undervoltage (ouv), output overvoltage (oov), adjustable high ? side current limit (i set and i lim ), and thermal shutdown (tsd). the ncp3011 includes a power good (pg) open drain output which flags out of regulation conditions. the operational transconductance amplifier (ota) provides a high gain error signal which is compared to the internal ramp signal using the pwm comparator. this results in a voltage mode pwm feedback stage. the pwm signal is sent to the internal gate drivers to modulate mosfet on and off times. the gate driver stage incorporates symmetrical fixed non ? overlap time between the high ? side and low ? side mosfet gate drives. the ncp3011 has a dual function master/slave sync pin in slave mode, the ncp3011 synchronizes to an external clock signal. in master mode, the ncp3011 can output a phase shifted clock signal to drive another master slave equipped power stage to provide a 180 switching relationship between the power stages. this can help to reduce the required input filter capacitance in multi ? stage power converters. the external 1.25 v reference voltage (vref) is provided for system level use. it remains active even when the ncp3011 is disabled. por and uvlo the device contains an internal power on reset (por) and input undervoltage lockout (uvlo) that inhibits the internal logic and the output stage from operating until v cc reaches their respective predefined voltage levels. the internal logic takes approximately 50 s to check the sync pin and determine if the device is in master mode or slave mode once the voltage at v cc exceeds the rising uvlo threshold. the device remains in standby if enable is not asserted following the 50 s time period. enable/disable the device has an enable pin (en) with internal 50 a pullup current. this gives the user the option of driving en with a push ? pull or open ? drain/collector enable signal. when driving en with an external logic supply a 10 k series current limiting resistor must be placed in series with en. see figure 27. the maximum enable threshold is 3.4 v. if no external drive voltage is available, the internal pullup can be used to enable the device, and an open drain/collector input, such as a mosfet or bjt can be used to disable the device. a capacitor connected between en and ground can be used with the internal pullup current source to provide a fixed delay to turn ? on and turn off. see equation 1. disable enable en v en ? or ? ? or ? disable enable disable enable 10 k enable logic figure 27. enable circuits: push ? pull, open ? drain, or open ? collector c en_dly i pu t en_dly v en_th (eq. 1) c en_dly = delay capacitance (f) i pu = pullup current v en_th = enable input high threshold voltage t en_dly = desired delay time
ncp3011, ncv3011 http://onsemi.com 12 startup and shutdown once enable is asserted the device begins its startup process. closed ? loop soft ? start begins after a 400 s delay wherein the boost capacitor is charged, and the current limit threshold is set. during the 400 s delay the ota output is set to just below the valley voltage of the internal ramp. this is done to reduce delays and to ensure a consistent pre soft ? start condition. the device increases the internal reference from 0 v to 0.8 v in 32 discrete steps while maintaining closed loop regulation at each step. some overshoot may be evident at the start of each step depending on the voltage loop phase margin and bandwidth. see figure 28. the total soft ? start time is 5.12 ms. the soft ? stop process begins once the en pin voltage goes below the input low threshold. soft ? stop decreases the internal reference from 0.8 v ? 0 v in 32 steps as with soft ? start. soft ? stop finishes with one ?last? high side gate pulse at half the period of the prior pulse. this helps ensure positive inductor current following turn off at light loads, which prevents negative output voltage. enable low during soft ? start will result in soft ? stop down counting from that step. likewise, enable high during soft ? stop will result in soft ? start up counting from that step. figure 28. soft ? start details internal reference voltage 25 mv steps 0.8 v 0v 0 .7v ota output internal ramp output voltage 32 voltage steps
ncp3011, ncv3011 http://onsemi.com 13 master/slave synchronization the sync pin performs two functions. the first function is to identify if the device is a master or a slave. the second function is to either synchronize to an external clock (slave mode) or provide an external clock that is shifted by 180 from the high side switch (master mode). the typical application circuit for this is shown in figure 29. sync 1 vin master sync 2 vin slave 60k hsdr hsdr figure 29. master slave typical application upon initial power up, the device determines if it is a master or slave by applying 1.25 v to the sync pin and determining whether the current draw from the pin is greater than the master threshold current (isync trip ). if isync trip is exceeded then the device enters master mode. if the current is less than isync trip the device enters slave mode. once identified as a master, the device switching frequency is increased by 15%. see equation 2. r master sync ref isync trip (eq. 2) r master = master select resistor ( ) sync ref = sync reference voltage (v) isync trip = master threshold current (a) figure 30. master slave typical waveforms master hsdrv slave hsdrv sync1 voltage sync 2 voltage sync 1 current sync 2 current time > 40 s vref = 1.25 v i trip = 10 a 0 a 0 ? 50% duty cycle indication of master indication of slave vref = 1.25 v pulse detect master detection time > 40 s hold result 40 s 0 ? 50% duty cycle slave pull down turn on input voltage
ncp3011, ncv3011 http://onsemi.com 14 the master slave identification begins when input voltage is applied prior to por. upon application of input voltage, the device waits for input pulses for a minimum of 40 s as shown in figure 30. during the pulse detection period if concurrent edges occur on the sync pin from an external source, the device enters slave mode and skips the master detection sequence. the device will remain in the detected state until power is cycled. gnd sync 1.21 v master detect & hold current sensor figure 31. sync_in sync_out external synchronization the device can sync to frequencies that are 15% to 60% higher than the nominal switching frequency. if an external sync pulse is present at the sync pin prior to input voltage application to the device, then no additional external components are needed. if the external clock is not present following power on reset of the device, the voltage on the sync pin will determine whether the device is a master or a slave. if the external clock source is meant to start after device operation, its off state should be high or tristate. it is also important to note that the slope of the internal ramp is fixed and synchronizing to a faster clock which will truncate the ramp signal. the equation for calculating the remaining ramp height is shown below: v ramp vramp typ * f nom f sync 1v* 400 khz 570 khz 0.70 v (eq. 3) oov, ouv, and power good the output voltage of the buck converter is monitored at the feedback pin of the output power stage. four comparators are placed on the feedback node of the ota to monitor the operating window of the feedback voltage as shown in figures 32 and 33. all comparator outputs are ignored during the soft ? start sequence as soft ? start is regulated by the ota and false trips would be generated. further, the power good pin is held low until the comparators are evaluated. after the soft ? start period has ended, if the feedback is below the reference voltage of comparator 4 (0.6 < v fb ), the output is considered ?undervoltage,? the device will initiate a restart, and the power good pin remains low with a 55 pulldown resistance. if the voltage at the feedback pin is between the reference voltages of comparator 4 and comparator 3 (0.60 < v fb < 0.72), then the output voltage is considered ?power not good low? and the power good pin remains low. when the feedback pin voltage rises between the reference voltages of comparator 3 and comparator 2 (0.72 < v fb < 0.88), then the output voltage is considered ?power good? and the power good pin is released. if the voltage at the feedback pin is between the reference voltages of comparator 2 and comparator 1 (0.88 < v fb < 1.00), the output voltage is considered ?power not good high? and the power good pin is pulled low with a 55 pulldown resistance. finally, if the feedback voltage is greater than comparator 1 (1.0 < v fb ), the output voltage is considered ?overvoltage,? the power good pin will remain low, and the device will latch off. to clear a latch fault, input voltage must be recycled. graphical representation of the oov, ouv, and power good pin functionality is shown in figures 34 and 35.
ncp3011, ncv3011 http://onsemi.com 15 vref = 0.8 v v7= vref * 75% v4 = vref * 110% v5 = vref * 90% v2 = vref * 125% comparator 1 comparator 2 comparator 3 comparator 4 logic soft start complete power good restart latch off fb figure 32. oov, ouv, and power good circuit diagram power good = 1 power good = 1 power good = 0 vref = 0.8 v vtrip_pg = vref * 110% voov = vref * 125% vtrip_pg = vref * 90% power good = 0 ouvp & power good = 0 oovp & power good = 0 trip level tolerance 2% hysteresis = 5 mv trip level tolerance 2% hysteresis = 5 mv trip level tolerance 2% hysteresis = 5 mv trip level tolerance 2% hysteresis = 5 mv power not good high power not good low figure 33. oov, ouv, and power good window diagram vouv = vref * 75%
ncp3011, ncv3011 http://onsemi.com 16 0.8 v ( vref * 100 %) 0.72 v (vref * 90%) 0.60 v (vref * 75%) 0.88 v (vref * 110 %) 1.0 v (vref * 125 %) fb voltage latch off power good reinitiate softstart softstart complete power good pin figure 34. powerup sequence and overvoltage latch 0.8 v (vref *100%) 0.72 v (vref *90%) 0.60 v (vref *75%) 0.88 v (vref *110%) 1.0 v (vref *125%) fb voltage latch off power good reinitiate softstart softstart complete power good figure 35. powerup sequence and undervoltage soft ? start
ncp3011, ncv3011 http://onsemi.com 17 current limit and current limit set overview the ncp3011 uses the voltage drop across the high side mosfet during the on time to sense inductor current. the i limit block consists of a voltage comparator circuit which compares the dif ferential voltage across the v cc pin and the v sw pin with a resistor settable voltage reference. the sense portion of the circuit is only active while the hs mosfet is turned on. control vset 6 rset iset 13 ua itrip ref ? 63 steps, 6.51 mv/step dac / counter ilim out hsdr lsdr vsw vin vcc itrip ref vsense switch cap figure 36. i set / i limit block diagram current limit set the i limit comparator reference is set during the startup sequence by forcing a typically 13 a current through the low side gate drive resistor. the gate drive output will rise to a voltage level shown in the equation below: v set i set *r set (eq. 4) where i set is 13 a and r set is the gate to source resistor on the low side mosfet. this resistor is normally installed to prevent mosfet leakage from causing unwanted turn on of the low side mosfet. in this case, the resistor is also used to set the i limit trip level reference through the i limit dac. the i set process takes approximately 350 s to complete prior to soft ? start stepping. the scaled voltage level across the i set resistor is converted to a 6 bit digital value and stored as the trip value. the binary i limit value is scaled and converted to the analog i limit reference voltage through a dac counter. the dac has 63 steps in 6.51 mv increments equating to a maximum sense voltage of 403 mv. during the i set period prior to soft ? start, the dac counter increments the reference on the i set comparator until it crosses the v set voltage and holds the dac reference output to that count value. this voltage is translated to the i limit comparator during the i sense portion of the switching cycle through the switch cap circuit. see figure 36. exceeding the maximum sense voltage results in no current limit. steps 0 to 10 result in an effective current limit of 0 mv. current sense cycle figure 37 shows how the current is sampled as it relates to the switching cycle. current level 1 in figure 37 represents a condition that will not cause a fault. current level 2 represents a condition that will cause a fault. the sense circuit is allowed to operate below the 3/4 point of a given switching cycle. a given switching cycle?s 3/4 t on time is defined by the prior cycle?s t on and is quantized in 10 ns steps. a fault occurs if the sensed mosfet voltage exceeds the dac reference within the 3/4 time window of the switching cycle.
ncp3011, ncv3011 http://onsemi.com 18 1/4 1/2 to n ? 1 1/4 3/4 to n ? to n ? 2 ? to n ? 1 no trip: vsense < i trip ref at 3/4 point trip: vsense > i trip ref at 3/4 point 3/4 3/4 point determined by prior cycle vsense 1/2 current level 2 current level 1 itrip ref figure 37. i limit trip point description each switching cycle?s ton is counted in 10 ns time steps. the 3/4 sample time value is held and used for the following cycle?s limit sample time soft ? start current limit during soft ? start the i set value is doubled to allow for inrush current to charge the output capacitance. the dac reference is set back to its normal value after soft ? start has completed. v sw ringing the i limit block can lose accuracy if there is excessive v sw voltage ringing that extends beyond the 1/2 point of the high ? side transistor on ? time. proper snubber design and keeping the ratio of ripple current and load current in the 10 ? 30% range can help alleviate this as well. current limit a current limit trip results in completion of one switching cycle and subsequently half of another cycle t on to account for negative inductor current that might have caused negative potentials on the output. subsequently the power mosfets are both turned off and a 4 soft ? start time period wait passes before another soft ? start cycle is attempted. i ave vs trip point the average load trip current versus r set value is shown the equation below: i avetrip i set r set r ds(on) 1 4 v in v out l v out v in 1 f sw
(eq. 5) where: l = inductance (h) i set = 13 a r set = gate to source resistance ( ) r ds(on) = on resistance of the hs mosfet ( ) v in = input voltage (v) v out = output voltage (v) f sw = switching frequency (hz) boost clamp functionality the boost circuit requires an external capacitor connected between the bst and v sw pins to store char ge for supplying the high and low ? side gate driver voltage. this clamp circuit limits the driver voltage to typically 7.5 v when v in > 9 v, otherwise this internal regulator is in dropout and typically v in ? 1.25 v. the boost circuit regulates the gate driver output voltage and acts as a switching diode. a simplified diagram of the boost circuit is shown in figure 38. while the switch node is grounded, the sampling circuit samples the voltage at the boost pin, and regulates the boost capacitor voltage. the sampling circuit stores the boost voltage while the v sw is high and the linear regulator output transistor is reversed biased. vin 8.9 v bst vsw lsdr figure 38. boost circuit switch sampling circuit
ncp3011, ncv3011 http://onsemi.com 19 reduced sampling time occurs at high duty cycles where the low side mosfet is of f for the majority of the switching period. reduced sampling time causes errors in the regulated voltage on the boost pin. high duty cycle / input voltage induced sampling errors can result in increased boost ripple voltage or higher than desired dc boost voltage. figure 39 outlines all operating regions. the recommended operating conditions are shown in region 1 (green) where a 0.1 f, 25 v ceramic capacitor can be placed on the boost pin without causing damage to the device or mosfets. larger boost ripple voltage occurring over several switching cycles is shown in region 2 (y ellow). the boost ripple frequency is dependent on the output capacitance selected. the ripple voltage will not damage the device or 12 v gate rated mosfets. conditions where maximum boost ripple voltage could damage the device or 12 v gate rated mosfets can be seen in region 3 (orange). placing a boost capacitor that is no greater than 10x the input capacitance of the high side mosfet on the boost pin limits the maximum boost voltage < 12 v. the typical drive waveforms for regions 1, 2 and 3 (green, yellow, and orange) regions of figure 39 are shown in figure 40. region 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 2 11 . 5v region 2 22v region 3 4 6 8 10 12 14 16 18 20 22 24 26 28 duty cycle input voltage normal operation increased boost ripple (still in specification) increased boost ripple capacitor optimization required 71% maxi mum duty cycle boost voltage levels max duty cycle figure 39. safe operating area for boost voltage with a 0.1 f capacitor
ncp3011, ncv3011 http://onsemi.com 20 figure 40. typical waveforms for region 1 (top), region 2 (middle), and region 3 (bottom) vboost vin 7.5v normal maximum vboost vin normal maximum 0v vboost vin 7.5v 7.5v 7.5v 7.5v 0v 7.5v 0v to illustrate, a 0.1 f boost capacitor operating at > 80% duty cycle and > 22.5 v input voltage will exceed the specifications for the driver supply voltage. see figure 41.
ncp3011, ncv3011 http://onsemi.com 21 boost voltage 0 2 4 6 8 10 12 14 16 18 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26.5 input voltage (v) boost voltage (v) (clarity on boost max and ripple def) figure 41. boost voltage at 80% duty cycle voltage ripple maximum allowable voltage maximum boost voltage inductor selection when selecting the inductor, it is important to know the input and output requirements. some example conditions are listed below to assist in the process. table 1. design parameters design parameter example value input voltage (v in ) 9 v to 18 v nominal input voltage (v in ) 12 v output voltage (v out ) 3.3 v input ripple voltage (vin ripple ) 300 mv output ripple voltage (vout ripple ) 50 mv output current rating (i out ) 8 a operating frequency (fsw) 400 khz a buck converter produces input voltage (v in ) pulses that are lc filtered to produce a lower dc output voltage (v out ). the output voltage can be changed by modifying the on time relative to the switching period (t) or switching frequency. the ratio of high side switch on time to the switching period is called duty cycle (d). duty cycle can also be calculated using v out , v in , the low side switch voltage drop v lsd , and the high side switch voltage drop v hsd . f 1 t (eq. 6) d t on t ( d t off t (eq. 7) d v out v lsd v in v hsd v lsd d v out v in (eq. 8) 27.5% 3.3 v 12 v the ratio of ripple current to maximum output current simplifies the equations used for inductor selection. the formula for this is given in equation 9. ra i i out (eq. 9) the designer should employ a rule of thumb where the percentage of ripple current in the inductor lies between 10% and 40%. when using ceramic output capacitors the ripple current can be greater thus a user might select a higher ripple current, but when using electrolytic capacitors a lower ripple current will result in lower output ripple. now, acceptable values of inductance for a design can be calculated using equation 10. l v out i out ra f sw ( 1 d ) 3.3 h (eq. 10) 3.3 v 8a 23% 400 khz ( 1 27.5% ) the relationship between ra and l for this design example is shown in figure 42.
ncp3011, ncv3011 http://onsemi.com 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 10% 15% 20% 25% 30% 35% 40% v in , (v) l, inductance ( h) 18 v v out = 3.3 v 15 v 12 v 9 v figure 42. ripple current ratio vs. inductance to keep within the bounds of the parts maximum rating, calculate the rms current and peak current. i rms i out 1 ra 2 12 8.02 a (eq. 11) 8a 1 (0.23) 2 12 (eq. 12) i pk i out 1 ra 2 8.92 a 8a 1 (0.23) 2 an inductor for this example would be around 3.3 h and should support an rms current of 8.02 a and a peak current of 8.92 a. the final selection of an output inductor has both mechanical and electrical considerations. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the lar gest components in the regulation system, a minimum inductor value is particularly important in space ? constrained applications. from an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by equation 13. slewrate lout v in v out l out 2.6 a s (eq. 13) 12 v 3.3 v 3.3 h this equation implies that larger inductor values limit the regulator?s ability to slew current through the output inductor in response to output load transients. consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. this results in larger values of output capacitance to maintain tight output voltage regulation. in contrast, smaller values of inductance increase the regulator?s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. the peak ? to ? peak ripple current for the ncp3011 is given by the following equation: i pp v out ( 1 d ) l out f sw (eq. 14) ipp is the peak to peak current of the inductor. from this equation it is clear that the ripple current increases as l out decreases, emphasizing the trade ? off between dynamic response and ripple current. the power dissipation of an inductor consists of both copper and core losses. the copper losses can be further categorized into dc losses and ac losses. a good first order approximation of the inductor losses can be made using the dc resistance as they usually contribute to 90% of the losses of the inductor shown below: lp cu i rms 2 dcr (eq. 15) the core losses and ac copper losses will depend on the geometry of the selected core, core material, and wire used. most vendors will provide the appropriate information to make accurate calculations of the power dissipation then the total inductor losses can be capture buy the equation below: lp tot lp cu_dc lp cu_ac lp core (eq. 16) input capacitor selection the input capacitor has to sustain the ripple current produced during the on time of the upper mosfet, so it must have a low esr to minimize the losses. the rms value of this ripple is: iin rms i out d ( 1 d ) (eq. 17) d is the duty cycle, iin rms is the input rms current, and i out is the load current. the equation reaches its maximum value with d = 0.5. loss in the input capacitors can be calculated with the following equation: p cin esr cin i in rms 2 (eq. 18) p cin is the power loss in the input capacitors and esr cin is the effective series resistance of the input capacitance. due to large di/dt through the input capacitors, electrolytic or ceramics should be used. if a tantalum must be used, it must by surge protected. otherwise, capacitor failure could occur. input start ? up current to calculate the input startup current, the following equation can be used. i inrush c out v out t ss (eq. 19) i inrush is the input current during startup, c out is the total output capacitance, v out is the desired output voltage, and t ss is the soft start interval. if the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used.
ncp3011, ncv3011 http://onsemi.com 23 output capacitor selection the important factors to consider when selecting an output capacitor is dc voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. the output capacitor must be rated to handle the ripple current at full load with proper derating. the rms ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies but a multiplier is usually given for higher frequency operation. the rms current for the output capacitor can be calculated below: co rms i o ra 12 (eq. 20) the maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the equivalent series inductance (esl) and esr. the main component of the ripple voltage is usually due to the esr of the output capacitor and the capacitance selected. v esr_c i o ra esr co 1 8 f sw co (eq. 21) the esl of capacitors depends on the technology chosen but tends to range from 1 nh to 20 nh where ceramic capacitors have the lowest inductance and electrolytic capacitors then to have the highest. the calculated contributing voltage ripple from esl is shown for the switch on and switch off below: v eslon esl i pp f sw d (eq. 22) v esloff esl i pp f sw ( 1 d ) (eq. 23) the output capacitor is a basic component for the fast response of the power supply. in fact, during load transient, for the first few microseconds it supplies the current to the load. the controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. during a load step transient the output voltage initially drops due to the current variation inside the capacitor and the esr (neglecting the effect of the effective series inductance (esl)). v out ? esr i tran esr co (eq. 24) a minimum capacitor value is required to sustain the current during the load transient without discharging it. the voltage drop due to output capacitor discharge is approximated by the following equation: v out ? dischg i tran 2 l out c out v in v out (eq. 25) in a typical converter design, the esr of the output capacitor bank dominates the transient response. it should be noted that vout ? discharge and vout ? esr are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the esl). conversely during a load release, the output voltage can increase as the energy stored in the inductor dumps into the output capacitor. the esr contribution from equation 21 still applies in addition to the output capacitor charge which is approximated by the following equation: v out ? chg i tran 2 l out c out v out (eq. 26) power mosfet selection power dissipation, package size, and the thermal environment drive mosfet selection. to adequately select the correct mosfets, the design must first predict its power dissipation. once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. power dissipation has two primary contributors: conduction losses and switching losses. the control or high ? side mosfet will display both switching and conduction losses. the synchronous or low ? side mosfet will exhibit only conduction losses because it switches into nearly zero voltage. however, the body diode in the synchronous mosfet will suffer diode losses during the non ? overlap time of the gate drivers. starting with the high ? side or control mosfet, the power dissipation can be approximated from: p d_control p cond p sw_tot (eq. 27) the first term is the conduction loss of the high ? side mosfet while it is on. p cond i rms_control 2 r ds(on)_control (eq. 28) using the ra term from equation 9, i rms becomes: (eq. 29) i rms_control i out d 1 ra 2 12 the second term from equation 27 is the total switching loss and can be approximated from the following equations. p sw_tot p sw p ds p rr (eq. 30) the first term for total switching losses from equation 30 includes the losses associated with turning the control mosfet on and off and the corresponding overlap in drain voltage and current. p sw p ton p toff (eq. 31) 1 2 i out v in f sw t on t off
ncp3011, ncv3011 http://onsemi.com 24 where: t on q gd i g1 q gd v bst v th r hspu r g (eq. 32) and: t off q gd i g2 q gd v bst v th r hspd r g (eq. 33) next, the mosfet output capacitance losses are caused by both the control and synchronous mosfet but are dissipated only in the control mosfet. p ds 1 2 q oss v in f sw (eq. 34) finally the loss due to the reverse recovery time of the body diode in the synchronous mosfet is shown as follows: p rr q rr v in f sw (eq. 35) the low ? side or synchronous mosfet turns on into zero volts so switching losses are negligible. its power dissipation only consists of conduction loss due to r ds(on) and body diode loss during the non ? overlap periods. p d_sync p cond p body (eq. 36) conduction loss in the low ? side or synchronous mosfet is described as follows: p cond i rms_sync 2 r ds(on)_sync (eq. 37) where: (eq. 38) i rms_sync i out ( 1 d ) 1 ra 2 12 the body diode losses can be approximated as: p body v fd i out f sw nol lh nol hl (eq. 39) vth figure 43. mosfet switching characteristics i g1 : output current from the high ? side gate drive (hsdr) i g2 : output current from the low ? side gate drive (lsdr) ? sw : switching frequency of the converter. v bst : gate drive voltage for the high ? side drive, typically 7.5 v. q gd : gate charge plateau region, commonly specified in the mosfet datasheet v th : gate ? to ? source voltage at the gate charge plateau region q oss : mosfet output gate charge specified in the data sheet q rr : reverse recovery charge of the low ? side or synchronous mosfet, specified in the datasheet r ds(on)_control : on resistance of the high ? side, or control, mosfet r ds(on)_sync : on resistance of the low ? side, or synchronous, mosfet nol lh : dead time between the lsdr turning off and the hsdr turning on, typically 85 ns nol hl : dead time between the hsdr turning off and the lsdr turning on, typically 75 ns once the mosfet power dissipations are determined, the designer can calculate the required thermal impedance for each device to maintain a specified junction temperature at the worst case ambient temperature. the formula for calculating the junction temperature with the package in free air is: t j t a p d r ja t j : junction temperature t a : ambient temperature p d : power dissipation of the mosfet under analysis r ja : thermal resistance junction ? to ? ambient of the mosfet?s package as with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e. worst case mosfet r ds(on) ).
ncp3011, ncv3011 http://onsemi.com 25 figure 44. mosfets timing diagram high ? side logic signal low ? side logic signal high ? side mosfet low ? side mosfet r dsmax r ds(on)min r dsmax r ds(on)min nol hl nol lh t f t d(on) t r t d(off) t r t f t d(on) t d(off) another consideration during mosfet selection is their delay times. turn ? on and turn ? off times must be short enough to prevent cross conduction. if not, there will be conduction from the input through both mosfets to ground. therefore, the following conditions must be met. t d(on)_control nol lh t d(off)_sync t f _sync (eq. 40) t (on)_sync nol hl t d(off)_control t f _control and the mosfet parameters, t d(on) , t r , t d(off) and t f are can be found in their appropriate datasheets for specific conditions. nol lh and nol hl are the dead times which were described earlier and are 85 ns and 75 ns, respectively. feedback and compensation the ncp3011 is a voltage mode buck convertor with a transconductance error amplifier compensated by an external compensation network. compensation is needed to achieve accurate output voltage regulation and fast transient response. the goal of the compensation circuit is to provide a loop gain function with the highest crossing frequency and adequate phase margin (minimally 45 ). the transfer function of the power stage (the output lc filter) is a double pole system. the resonance frequency of this filter is expressed as follows: f p0 1 2 l c out (eq. 41) parasitic equivalent series resistance (esr) of the output filter capacitor introduces a high frequency zero to the filter network. its value can be calculated by using the following equation: f z0 1 2 c out esr (eq. 42) the main loop zero crossover frequency f 0 can be chosen to be 1/10 ? 1/5 of the switching frequency. table 2 shows the three methods of compensation. table 2. compensation types zero crossover frequency condition compensation type typical output capacitor type f p0 < f z0 < f 0 < f s /2 type ii electrolytic, tantalum f p0 < f 0 < f z0 < f s /2 type iii method i tantalum, ceramic f p0 < f 0 < f s /2 < f z0 type iii method ii ceramic
ncp3011, ncv3011 http://onsemi.com 26 compensation type ii this compensation is suitable for electrolytic capacitors. components of the type ii compensation (figure 45) network can be specified by the following equations: figure 45. type ii compensation r c1 2 f 0 l v ramp v out esr v in v ref gm (eq. 43) c c1 1 0.75 2 f p0 r c1 (eq. 44) c c2 1 r c1 f s (eq. 45) r1 v out v ref v ref r2 (eq. 46) v ramp is the peak ? to ? peak voltage of the oscillator ramp and gm is the transconductance error amplifier gain. capacitor c c2 is optional. compensation type iii tantalum and ceramics capacitors have lower esr than electrolytic, so the zero of the output lc filter goes to a higher frequency above the zero crossover frequency. this requires a type iii compensation network as shown in figure 46. there are two methods to select the zeros and poles of this compensation network. method i is ideal for tantalum output capacitors, which have a higher esr than ceramic: figure 46. type iii compensation f z1 0.75 f p0 (eq. 47) f z2 f p0 (eq. 48) f p2 f z0 (eq. 49) f p3 f s 2 (eq. 50) method ii is better suited for ceramic capacitors that typically have the lowest esr available: f z2 f 0 1 sin max 1 sin max (eq. 51) f p2 f 0 1 sin max 1 sin max (eq. 52) f z1 0.5 f z2 (eq. 53) f p3 0.5 f s (eq. 54) max is the desired maximum phase margin at the zero crossover frequency, ? 0 . it should be 45 ? 75 . convert degrees to radians by the formula: max max degress 2 360 :units radians (eq. 55) the remaining calculations are the same for both methods. r c1 2 gm (eq. 56) c c1 1 2 f z1 r c1 (eq. 57) c c2 1 2 f p3 r c1 (eq. 58) c fb1 2 f 0 l v ramp c out v in r c1 (eq. 59) r fb1 1 2 c fb1 f p2 (eq. 60) (eq. 61) r1 1 2 c fb1 f z2 r fb1 r2 v ref v out v ref r1 (eq. 62) if the equation in equation 63 is not true, then a higher value of r c1 must be selected. r1 r2 r fb1 r1 r fb1 r2 r fb1 r1 r2 1 gm (eq. 63)
ncp3011, ncv3011 http://onsemi.com 27 typical application circuit 9 ? 16 v vcc bst hsdr vsw lsdr comp fb 3.3 v c bst q2 q1 3.3 uh r iset r fb1 c out ? 2/3 c c1 r c c c2 gnd r fb2 c in ? 1/2 r gs r fb3 c fb d1 c in ? 3/4 c in ? 5 c out ? 1 r g ncp3011 figure 47. typical application, v in = 9 ? 16 v, v out = 3.3 v, i out = 6 a reference designator value cin ? 1 470 f cin ? 2 470 f cin ? 3 22 f cin ? 4 22 f cin ? 5 1 f cc1 56 pf cc2 12 nf cfb 1.0 nf cout1 470 f cout2 22 f cout3 22 f cbst 0.1 f rc 4.81 k rg 0 rgs 1.0 k riset 22.1 k rfb1 3.16 k rfb2 1.0 k rfb3 1.0 k q1 ntms4816n q2 ntms4816n d1 bat54
ncp3011, ncv3011 http://onsemi.com 28 package dimensions tssop ? 14 case 948g ? 01 issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp3011/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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